Mr. Telajala Venkata Mahendra
Full-Time Scholar
telajalamahendra@nitm.ac.in
+91-8985843575
Area of Research : Low-power VLSI
Content Addressable Memory
Digital Circuit Design
Non Volatile Memory Design
Experience :
- Achieved 94% in NPTEL Online Certification Course On "Digital Circuits And Systems" Conducted By IIT Madras
- Achieved 3rd Prize in Technical Quiz at NIT Meghalaya
- Presented “Brain Finger printing Technology” at Newtons Group of Institutions and won first prize.
- Member of “Training and Placement Cell” & “Student Council” in NIT Meghalaya during 2015-2016
Conference Attended :
- Participated in the Instruction Enhancement Programme (IEP) on High Level Design to Silicon under SMDP-C2SD held during 24th to 27th February 2018, organized by the Department of Electronics and Communication Engineering, IIT Roorkee in association with Ministry of Electronics and Information Technology (Meity), GOI
- Participated in the workshop on High-Speed Communication Circuits under SMDP-C2SD held during 25th to 30th June 2018, organized by the Department of Electronics and Communication Engineering, IIT Guwahati
- Participated and Assisted Lab Sessions in Short Term Training Programme on Digital Design and Analysis at Backend Level Using CADENCE sponsored by TEQIP-III & SERB-DST held during 5th to 9th March 2018, organized by the Department of Electronics and Communication Engineering, NIT Meghalaya
- Participated in 2-Day Familiarization Workshop on Nanofabrication Technologies by Indian Nano electronics Users Programme (INUP) at IIT Bombay and IISc
- IEEE International Conference on Innovations in Electronics, Signal Processing and Communication (IESC 2017) during 6-7 April 2017
- IEEE International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV 2015) during 29-30 January 2015
- Attended Workshop on Future Challenges in Wireless Communication and Signal Processing at NIT Meghalaya
- Attended Workshop on Printed Circuit Board (PCB) Design & Fabrication at NIT Meghalaya
- Participated in Paper Presentation Contests at various colleges in National level Techfests.
Publications : Journal
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat,“Precharge Free Dynamic Content Addressable Memory”, IET Electronics Letters,vol. 54, no. 9, pp. 556 558, May 2018.
- T. V. Mahendra, S. Mishra, and A. Dandapat, “Self controlledhigh performance pre-charge free content addressable memory”, IEEE Transactionson Very Large Scale Integration (VLSI) Systems, vol. 25, no. 8, pp. 2388 -2392, Aug. 2017.
- S. Mishra, T. V. Mahendra, J. Saikia, and A. Dandapat, “ALow-Overhead Dynamic TCAM with Pipelined Read-Restore Refresh Scheme,” IEEETrans. Circuits Syst. I, Reg. Papers, vol. 65, no. 5, pp. 1591-1601, May 2018.
- S. Mishra, T. V. Mahendra, and A. Dandapat,``A 9-T 833-MHz1.72-fJ/Bit/Search Quasi Static Ternary Fully Associative Cache Tag withSelective Matchline Evaluation for Wire Speed Applications,” IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 63, no. 11, pp. 1910-1920, Nov. 2016.
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat,`` Match-Line Division and Control to Reduce Power Dissipation in ContentAddressable Memory”, IEEE Transactions on Consumer Electronics, Vol. 64, Issue3, pp-early access , 2018.
Conference
- T. V. Mahendra, S. Mishra, and A. Dandapat “Fully DynamicHigh Density Associative Storage Architectures: Study, Comparison and aProposal,” IEEE 3rd International Conference on Electronics and CommunicationSystems (ICECS 2016), 2016.
- K. B. Singh, T. V. Mahendra, K. R. Singh, and Ch. V. RamaRao, Image Enhancement with the Application of Local and Global EnhancementMethods for Dark Images, IEEE International Conference on Innovations in Electronics,Signal Processing and Communication (IESC 2017), Period -April 6-7, Place-Shillong, 2017.
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- K. B. Singh, S. W. Hussain, T. V. Mahendra and Ch. V. RamaRao, Implementation of OFDM and Pulsed-OFDM, IEEE 15th International Conferenceon Information Technology (ICIT), Period -Dec. 22-24, Place -Bhubaneswar, 2016.